Huan-lin Chang
Compact Device Modeling, Design Technology Platform
San Jose, California, United States
Summary
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Senior🎓
Top SchoolHuan-lin Chang is a compact device modeling expert with 18 years of SPICE and Verilog-A experience, currently driving modeling and design-technology platform work at Intel in San Jose. He has delivered production SPICE models across planar and FinFET nodes from 20nm to 7nm, and built statistical, corner, noise, LDE and post-layout modeling solutions for foundries and design signoff. As a former BSIM group manager at UC Berkeley and director at ProPlus, he has led cross-continental teams and grew an SDEP business to seven-figure POs while productizing automation tools for major foundry customers. He blends deep device physics, practical scripting (Python, PERL, MATLAB) and simulator expertise (HSPICE, Spectre, Eldo) to shorten turnaround and improve QA in model releases. An IEEE Senior Member, he is equally comfortable resolving model-implementation bugs with foundries and publishing technical manuals for community use. Notably, he has a track record of translating research-grade BSIM enhancements into production-ready EDA workflows and commercial products.
10 years of coding experience
7 years of employment as a software developer
Doctor of Philosophy (PhD) Electronics Engineering, Doctor of Philosophy (PhD) Electronics Engineering at National Taiwan University
Chinese, EnglishGithub contributions (5)
huanlinberkeley/pycmg
Dec 2018 - Aug 2021
Contributions:4 commits, 7 pushes, 1 branch in 2 years 8 months
huanlinberkeley/pybulk
Aug 2021 - Aug 2021
Contributions:12 pushes, 1 branch in 14 days
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