Summary
Hui S is a hardware verification and design engineer with 8 years of experience, currently an SMTS at AMD specializing in SAT-level verification using UVM and SystemVerilog. She has a strong track record across major firms (Oracle, Western Digital, Intel) building testbenches, checkers, scoreboards, and managing regressions and test matrices, and she also supports FPGA protolink flows. Hui pairs hands-on RTL-facing verification skills with schematic and physical design experience from academic projects, making her effective at bridging design and verification. On GitHub she has contributed to the well-known ACRN hypervisor project, improving C code quality and MISRA-C compliance—an indicator of attention to safety and standards beyond her hardware focus. Colleagues describe her as responsible, reliable, quick to learn, and effective at turning complex verification requirements into maintainable, auditable test environments.
8 years of coding experience
5 years of employment as a software developer
Master's degree, Electrical and Electronics Engineering, Master's degree, Electrical and Electronics Engineering at University of Southern California
Microelectronics and Solid State Electronics, Microelectronics and Solid State Electronics at East China Normal University
English