Huiyan Cheah
MTS Silicon Design Engineer at AMD
Singapore
Summary
👤
Senior🎓
Top SchoolHuiyan Cheah is a silicon design engineer with 13 years of experience specializing in front-end FPGA integration and full-chip RTL integration for programmable devices. Currently at AMD after five years at Xilinx, she builds integration flows, sanity checks, and infrastructure for next-generation FPGAs while liaising closely with stakeholders and mentoring team members. Her background blends seven years of academic research—culminating in a PhD—with hands-on expertise in Verilog/SystemVerilog, FPGA toolchains (Xilinx, Altera), HDL simulation, and automation using shell and Python. She’s equally comfortable debugging low-level boot-up issues on Virtex and Stratix platforms as she is designing testbenches and bus functional models, giving her a rare end-to-end view from RTL to bitstream. Notably, her career path reflects a strong bridge between rigorous research and production-grade silicon delivery, enabling pragmatic solutions grounded in deep technical understanding.
13 years of coding experience
12 years of employment as a software developer
Doctor of Philosophy (PhD), Doctor of Philosophy (PhD) at Nanyang Technological University
English, Chinese, MalayGithub contributions (1)
warclab/idea
Jan 2013 - Jun 2016
Contributions:17 commits, 5 pushes, 4 comments in 3 years 5 months
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