Ian Chuang
Senior Staff Engineer, Performance Architecture at SiFive
Taiwan
Summary
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Senior🎓
Top SchoolIan Chuang is a compute architect with 9 years of experience specializing in performance architecture for AI/ML accelerators and high-performance CPUs. He currently leads a performance architecture team at SiFive, driving cycle-accurate modeling, microarchitecture exploration, and performance targets across vector and matrix engines for Gen-2 and Gen-5 portfolios. His background spans SoC-level design and RTL sign-off at Qualcomm and MediaTek, where he integrated Arm clusters, developed DVFS co-processors, and established IP interconnect and QA flows. Ian combines hands-on RTL and ESL performance simulation expertise with product-focused architecture decisions that bridge silicon, firmware, and software teams. Based in Taiwan, he is notable for correlating high-fidelity models to RTL to ensure architectural accuracy across OoO cores up to 1024-bit vector lengths. Colleagues describe him as a pragmatic technical leader who turns complex microarchitectural trade-offs into measurable system gains.
9 years of coding experience
9 years of employment as a software developer
Master of Science (M.S.), Electrical Engineering, Master of Science (M.S.), Electrical Engineering at National Taiwan University of Science and Technology
Chinese, EnglishGithub contributions (2)
ianhchuang/EPC-Gen2-RFID-Tag-Baseband-Processor
Jan 2017 - Dec 2021
Contributions:50 commits, 49 pushes, 1 branch in 4 years 11 months
Gurint/RFID-Tag-Baseband-Processor
Jan 2017 - Jan 2017
Contributions:1 branch in 1 day
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