Summary
Ian Frasch is a DSP and digital hardware engineer with a decade of experience designing and implementing signal-processing algorithms on FPGAs and ASICs for satellite communications and image compression systems. He has led cross-disciplinary teams to deliver TX/RX satellite systems on Versal FPGAs, authored reusable HDL libraries (including resource-efficient decimators and parallel FIR generators), and accelerated a JPEG2000 compressor to 5x performance through algorithmic and HDL rework. Comfortable moving between MATLAB models, SystemVerilog, and production FPGA constraints, Ian bridges algorithm development and low-level hardware optimization while mentoring junior engineers and contributing to hiring. Based in Denver, he combines hands-on prototyping (early work included a continuous-phase FSK modem demo on BladeRF at DEF CON) with program-level coordination across RF, FPGA, software, and subcontractors. Known for pragmatic tradeoffs—like time-sharing DSP slices across clocks to save resources—he excels at turning complex signal-processing requirements into deployable, resource-aware hardware.
9 years of coding experience
9 years of employment as a software developer
Bachelor of Science / Master of Science dual degree Computer Engineering, Bachelor of Science / Master of Science dual degree Computer Engineering at Rochester Institute of Technology