Summary
Indrajit Paul is a Senior RTL/FPGA Design Engineer based in India with 11 years of hands-on experience in VHDL, Verilog and embedded C across Xilinx, Intel (Arria), and custom FPGA platforms. He has delivered complex PCIe DMA and memory interface designs, created IP packages, and led block-level Vivado projects including pin allocation, simulation and hardware debugging for XCKU15P-class devices. His background spans end-to-end hardware and firmware work—from analog and power design to high-speed digital protocols like MIPI CSI-2—reflecting rare full-stack hardware fluency. Comfortable in both consultancy and product teams, he combines practical FPGA implementation skills with system-level tradeoff analysis (latency, buffering and DMA strategy). An early maker and trainer, he also brings teaching and freelance project experience that sharpens his ability to communicate complex designs to cross-functional teams.
11 years of coding experience
6 years of employment as a software developer
Bachelor's Degree Applied Electronics & Instrumentation Engineer, Bachelor's Degree Applied Electronics & Instrumentation Engineer at University Institute of Technology, The University of Burdwan
Bengali, English, German