Ioannis Papadogiannis is a Digital IC Lead with over a decade of R&D experience designing low-power and high-speed digital silicon for top-tier customers, currently leading digital design efforts at Renesas after roles at Adveos, Apple, and Intel. He combines deep RTL expertise in power management and transceivers with hands-on system integrations, having delivered multiple successful products and RTL for FPGA and ASIC flows. Comfortable working with international teams, he pairs strong communication skills with practical delivery focus and customer-facing quality assurance. An active contributor to embedded open-source (notably adding peripheral, crypto and DMA support for the Zephyr RTOS on Renesas Smartbond platforms), he bridges firmware, device-tree/board bring-up and silicon design in a way few digital leads do.
10 years of coding experience
13 years of employment as a software developer
Master of Science - MS Electrical and Computer Engineering, Master of Science - MS Electrical and Computer Engineering at University of Patras
Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
Role in this project:
Embedded Systems Engineer / IoT Developer
Contributions:276 reviews, 35 PRs, 275 comments in 1 year 10 months
Contributions summary:Ioannis's contributions primarily focus on adding support for various peripherals within the Zephyr RTOS for the Renesas Smartbond DA1469x platform. They added support for Global Foundries silicon variants and the RTC peripheral. Additionally, they added support for the crypto and DMA accelerators. The user's work involves device tree updates and board configurations to integrate and enable these peripherals.
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Ioannis Papadogiannis - Digital IC Lead at Renesas Electronics