Ivan Shevchuk
FPGA Design Engineer at Quantstellation
Saint Petersburg, Saint Petersburg, Other
Summary
👤
Senior🎓
Top SchoolIvan Shevchuk is an FPGA Design Engineer with over 8 years focused on FPGA design and 12 years of professional experience overall, based in Saint Petersburg. He has built high-performance Ethernet packet-processing firmware for 1G–100G links, contributing to commercial test and analyzer products such as Bercut and Metrotek B100 lines. At Quantstellation since 2017 he continues to develop complex digital systems, bringing practical expertise in TWAMP, RFC2544, BERT and load-balancing filter implementations. Ivan combines deep protocol-level knowledge with hands-on hardware firmware development, and a background in network security from Saint Petersburg University of Telecommunications. He’s comfortable taking legacy projects through porting and bugfix cycles as well as designing new FPGA-based solutions that maximize throughput and determinism. An engineer who prefers systems-level challenges, he’s as likely to optimize packet pipelines as to root-cause intermittent timing issues in silicon-constrained designs.
11 years of coding experience
6 years of employment as a software developer
Specialist, Network Security, Specialist, Network Security at Saint Petersburg University of Telecommunications
English, Russian
Github Skills (6)
verilog8
systemverilog8
xilinx7
fpga6
pattern2
bloom1
Programming languages (1)
Github contributions (5)
johan92/verilog-coding-style
Apr 2016 - Jul 2018
Verilog (SystemVerilog) coding style
Contributions:10 commits, 9 pushes, 1 branch in 2 years 3 months
systemverilogverilog
johan92/fpga-hash-table
Aug 2015 - Apr 2016
Contributions:50 commits, 48 pushes, 2 branches in 8 months
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