Iztok Jeras
FPGA Design Engineer at Cosylab
Ljubljana, Slovenia
Summary
👤
Senior🎓
Top SchoolIztok Jeras is an FPGA and ASIC design engineer with 17 years of hands-on experience building and verifying complex digital systems, from SoC image streaming protocols to Zynq-based embedded platforms. Currently at Cosylab, he focuses on FPGA digital design, verification, digital library maintenance and Petalinux, bringing a pragmatic preference for short, well-documented code and up-to-date toolchains. His career spans FPGA, ASIC and SOC roles (including MIPI, AXI4-Stream, SPARC and ARC subsystems) and practical work on build systems, device trees and kernel/user-space drivers at Red Pitaya. An active open-source contributor, he has improved core oscilloscope FPGA controllers and SCPI parsers, emphasizing backward compatibility and robust parsing for 64-bit and floating-point data. Trained in cellular automata and discrete dynamic systems, he combines rigorous academic thinking with broad low-level programming fluency across dozens of languages and assembly flavors. Based in Ljubljana, he enjoys applying theoretical models like cellular automata to practical hardware problems, reflecting a curiosity that drives continual learning.
17 years of coding experience
15 years of employment as a software developer
Master’s Degree, cellular automata, discrete dynamic systems, 9, Master’s Degree, cellular automata, discrete dynamic systems, 9 at University of Ljubljana, Faculty of Computer and Information ScienceBachelor's Degree, Telecommunications Engineering, Bachelor's Degree, Telecommunications Engineering at University of Ljubljana ,Faculty of Electrical Engineering
Slovenian, Italian, English
Stackoverflow
81reputation
11kreached
4answers
5questions
Github Skills (19)
parser10
parsec10
c1110
sc10
c1710
parse10
fpga10
par10
float329
hardware9
floating-point9
controls9
testing8
sparc6
zynq6
Programming languages (14)
Github contributions (5)
RedPitaya/RedPitaya
Feb 2015 - Nov 2017
Role in this project:
Back-end Developer
Back-end DeveloperContributions:6582 commits, 15 PRs, 216 pushes in 2 years 9 months
Contributions summary:Iztok reverted a code change that removed deprecated acquisition code, indicating a focus on maintaining backward compatibility and ensuring existing functionality remains intact. The user's involvement appears to be within the scope of the oscilloscope FPGA controller, as demonstrated by the code differences in the `fpga_osc.c` file. This suggests the user is contributing to the core functionality and maintenance of the oscilloscope's FPGA control logic.
pitayaedaecosystemhardwarejava
j123b567/scpi-parser
Oct 2015 - Jul 2017
Open Source SCPI device library
Role in this project:Back-end Developer
Back-end DeveloperContributions:21 commits, 4 PRs, 10 comments in 1 year 9 months
Contributions summary:Iztok focused on improving the SCPI parser library, primarily targeting integer parsing functionality. They fixed buffer sizes for 64-bit integers and removed erroneously added functions. Further contributions include adding support for floating-point numbers and refining tests by incorporating C99 standards and snprintf for string formatting. These changes enhance the library's capabilities and improve its reliability.
scpiandroidparser-libraryscpi-parser
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