Jack Koenig
Senior Staff Engineer at SiFive
Berkeley, California, United States
Summary
🤩
Rockstar🎓
Top SchoolJack Koenig is a Senior Staff Engineer in Berkeley with a decade of experience building and hardening hardware design tooling and system-level RTL infrastructure. At SiFive he has progressed from contractor to senior staff, focusing on Chisel/FIRRTL ecosystems, Rocket Chip, and cache/system behavior—contributions that blend compiler-front-end parsing, backend optimizations, and build/CI automation. His open-source work on high-profile projects like chipsalliance/chisel and firrtl includes parser implementations with ANTLR4, performance improvements, and CI/CD modernization, reflecting deep fluency in Scala-based EDA stacks. Known humorously on GitHub as a "full stack bug developer," he pairs pragmatic bug fixes with architectural thinking to keep complex hardware generators reliable. He holds an MS in Computer Architecture from UC Berkeley and a BS in Computer Engineering from UT Austin, and brings both research-era power modeling insight and production-grade systems engineering to chip design toolchains.
10 years of coding experience
6 years of employment as a software developer
Master of Science - MS, Computer Architecture, Master of Science - MS, Computer Architecture at University of California, BerkeleyBS, BA, Computer Engineering, Plan II Honors, BS, BA, Computer Engineering, Plan II Honors at The University of Texas at AustinInformatics, Informatics at The University of Edinburgh
Stackoverflow
5,930reputation
108kreached
180answers
14questions
scala
top-5%
Github Skills (25)
parser10
risc-v10
sbt10
firrtl10
intermediate-code10
scala10
compiler-design10
parsing10
computer-engineering10
intermediate-language10
parse10
antlr10
build-automation10
chisel10
rt10
Programming languages (15)
Github contributions (5)
chipsalliance/chisel
Oct 2015 - Jan 2023
Chisel: A Modern Hardware Design Language
Role in this project:
Software Engineer
Software EngineerContributions:35 releases, 2164 reviews, 1059 commits in 7 years 4 months
Contributions summary:Jack contributed to the Chisel project, a hardware description language. Their work included enhancing and optimizing the project, such as, supporting different data types, improving existing APIs, and adding support for new features. They also made performance enhancements to key parts of the codebase. The user addressed various issues by adding enhancements to the codebase.
rtlasicvhdllanguage-designeda
chipsalliance/firrtl
Oct 2015 - Jan 2023
Flexible Intermediate Representation for RTL
Role in this project:Backend Developer
Backend DeveloperContributions:9 releases, 242 reviews, 774 commits in 7 years 4 months
Contributions summary:Jack contributed to the development of the Scala implementation of the FIRRTL intermediate representation (IR), parser, and serialization. Their work involved implementing a parser for the FIRRTL language using ANTLRv4, contributing to the core components of the compiler and the intermediate representation. The contributions included handling of types and declarations, creating the structure of the modules, as well as other utilities used by the compiler.
representationtransformationintermediate-representationrtlcompiler
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