Jaeduk Han
Research Scientist at Hanyang University
Seoul, Korea, Republic of
Summary
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SeniorJaeduk Han is an associate professor and mixed-signal engineer with nine years of professional experience spanning academia and industry, including roles at Hanyang University and Apple. He holds a Ph.D. in Electrical and Electronics Engineering from UC Berkeley and advanced degrees from Seoul National University, blending deep research credentials with hands-on chip design. His work focuses on automated analog layout tools—he developed LAYGO and LAYGO2 and contributed to BAG—reflecting a rare mix of EDA tooling and circuit-level expertise. Prior internships and engineering roles at Intel Labs, Xilinx, Altera, and TLi gave him broad exposure to semiconductor design and verification workflows. Based in Seoul, he runs a lab (Mighty Nifty Chips!) that bridges open-source tooling and academic research, often turning research prototypes into practical developer tools. Colleagues describe him as someone who translates complex analog design constraints into usable automation that accelerates chip design cycles.
10 years of coding experience
Github Skills (10)
virtuoso7
pdk7
cadence-virtuoso7
skill6
hardware6
python5
asic5
cadence5
cds4
craftcms3
Programming languages (3)
Github contributions (5)
niftylab/laygo2
Jun 2022 - Dec 2022
LAYout with Gridded Objects v2
Contributions:1 release, 190 commits, 14 PRs in 5 months
griddedlayout
ucb-art/laygo_obsolete
Dec 2016 - Mar 2017
Contributions:311 pushes, 1 branch, 3 issues in 2 months
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