Jakov Vrdoljak is an Electronics Engineer with 10 years of hands-on experience spanning analog/mixed-signal IC design, embedded systems, and power systems simulation. Currently an EE Designer focusing on simulations at Yazaki EMEA, he has practical exposure across startups and industry leaders including Rimac Technology and Innovation Centre Nikola Tesla. Jakov contributed backend enhancements to the pandapower open-source library, adding a more efficient power flow algorithm and zip load support, reflecting a blend of software fluency and power-systems knowledge. He holds advanced studies from FER and Wrocław University of Science and Technology, grounding his work in both theory and implementation. Known for bridging IC layout, EMC-aware embedded hardware, and simulation tooling, he often moves between low-level hardware detail and algorithmic improvements. Based in Zagreb, he combines pragmatic engineering with a track record of shipping measurable simulation and embedded improvements in multidisciplinary teams.
10 years of coding experience
2 years of employment as a software developer
Master's degree Electronics, Master's degree Electronics at Wrocław University of Science and Technology
Master's degree Electrical engineering and informaton technology, Master's degree Electrical engineering and informaton technology at FER
Convenient Power System Modelling and Analysis based on PYPOWER and pandas
Role in this project:
Back-end Developer
Contributions:84 commits, 8 PRs, 24 pushes in 5 years 1 month
Contributions summary:Jakov's commits primarily focused on implementing and enhancing core functionalities within the pandapower library. They added a new power flow algorithm, likely a more efficient sparse version, and integrated zip loads for Newton-Raphson power flow. The contributions involve modifications to existing modules and the addition of new files, indicating a focus on expanding the library's power system analysis capabilities.
Contributions:18 pushes, 1 branch in 4 years 2 months
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