Jakub Cabal
Team Leader, FPGA Engineer And Researcher at CESNET
Brno, South Moravia, Czechia
Summary
👤
Senior🎓
Top SchoolJakub Cabal is a team leader and FPGA engineer with 11 years of experience, specializing in high-speed network traffic processing and advanced FPGA implementations such as 400G Ethernet and PCIe Gen5. Based in Brno, he has worked at CESNET since 2014 and leads a small team developing low-latency, high-efficiency FPGA firmware and hardware, including a 400 Gbps packet DMA controller. His deep VHDL expertise and long-term stewardship of the Liberouter-related firmware reflect a strong practical research-to-production pipeline. He publishes regularly at leading FPGA conferences, bridging academic insight with real-world network infrastructure demands. Beyond hands-on design, he mentors junior engineers and shapes team practices to push performance limits. Colleagues value his mix of experimental research mindset and disciplined engineering that delivers measurable throughput and latency gains.
11 years of coding experience
Inženýr (Ing.), Inženýr (Ing.) at Vysoké učení technické v Brně
English, Czech
Github Skills (22)
uart10
simulation10
controller10
spi10
vhdl10
ethernet10
ghdl10
fpga10
accelerometer10
sphinx-extension9
documentation-generator8
driver7
firewall6
sphinx6
eda5
Programming languages (7)
Github contributions (5)
jakubcabal/pipemania-fpga-game
Jun 2015 - Dec 2018
Contributions:38 commits, 21 pushes, 2 branches in 3 years 6 months
jakubcabal/uart-for-fpga
Jul 2015 - Aug 2021
Simple UART controller for FPGA written in VHDL
Contributions:4 releases, 67 commits, 4 PRs in 6 years 1 month
fpgauartvhdluart-controllercontroller
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