Jannis Harder
Software Engineer For Formal Verification Tools
Leipzig, Saxony, Germany
Summary
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Rockstar🎓
Top SchoolJannis Harder is a software engineer with 13 years of experience specializing in formal verification tools and low-level systems development, currently contributing to YosysHQ from Leipzig. He combines deep expertise in assembler and synthesis toolchains—demonstrated by substantial backend contributions to the Yasm assembler and the widely used Yosys Open Synthesis Suite—with a pragmatic focus on reliability, performance, and correct-by-construction tooling. Jannis has implemented nuanced features such as virtual segment address handling, expression simplification for segment operations, and resilient bounded model checking workflows that keep analyses running after failed assertions. As a long-term self-employed engineer since 2016, he brings independent problem-solving and production-focused craftsmanship to open-source and commercial projects alike. Trained in computer science at Universität zu Lübeck, he pairs academic grounding with hands-on improvements to foundational verification infrastructure.
13 years of coding experience
Bachelor of Science (B.Sc.), Computer Science, Bachelor of Science (B.Sc.), Computer Science at Universität zu Lübeck
English, German
Github Skills (15)
c1710
verilog10
yosys10
assembly10
formal-verification10
c1110
assemble10
assembler10
optimization10
python9
data-structure9
data-structures9
c-language8
algorithms8
cprogramming-language8
Programming languages (14)
Github contributions (5)
YosysHQ/yosys
Mar 2022 - Jan 2023
Yosys Open SYnthesis Suite
Role in this project:
Back-end Developer
Back-end DeveloperContributions:51 reviews, 169 commits, 171 PRs in 10 months
Contributions summary:Jannis contributed to the Yosys Open SYnthesis Suite by implementing features and fixing bugs related to the smtbmc backend. Their work includes adding an option to continue BMC after failed assertions, fixing a typo in help text, avoiding unnecessary deep copies, fixing BMC with no assertions, adding -keep-going option and implementing new Yosys witness files. These commits showcase a focus on improving the tool's functionality and reliability within the context of formal verification.
synthesispythonsuiteyosys
yasm/yasm
Jul 2012 - Aug 2012
Yasm Assembler mainline development tree
Role in this project:Back-end Developer
Back-end DeveloperContributions:8 commits, 1 comment in 8 days
Contributions summary:Jannis primarily focused on enhancing the Yasm assembler's functionality by implementing and optimizing features related to section handling and address generation. They added the `vseg` section option and related calculations for virtual segment addresses, modifying core data structures and output mechanisms for map files. Furthermore, the user improved expression simplification, particularly for segment operations, to lift segoffs to the root. Finally, they added support for overriding value finalization in the bin objfmt, demonstrating a strong focus on low-level assembler design.
assemblermainline
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