Jared Barócsi - Software Engineer

Jared Barócsi

Software Engineer

Citrus Heights, California, United States

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Summary

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Rockstar

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Top School

Jared Barócsi is a software engineer and UC Davis computer science undergraduate with five years of engineering experience focused on computer architecture and hardware-aware software. He has hands-on experience in C++, C, Java, Scala, C#, and Python, and has worked with Chisel and FIRRTL to synthesize and debug modular memory systems for the DINOCPU model, simulating delayed memory and cache behavior. As an active contributor to the widely used Chisel and FIRRTL projects, he implemented serialization, memory-access APIs, and bug fixes that improved compiler reliability and memory annotation handling. Formerly a SiFive platform engineer, Jared combines research collaboration with practical backend development and maintains a professional open-source footprint while moving future work to a personal GitHub. Based in Citrus Heights, CA, he’s seeking research or internship roles that bridge computer architecture research and engineering implementation.

5 years of coding experience

University of California, Davis

Github Skills (16)

scala10

compiler10

data-serialization10

compiler-compiler10

firrtl10

intermediate-language10

intermediate-code10

transformation10

chisel10

serialization10

hardware9

testing9

chip89

generator9

verilog8

Programming languages (2)

ScalaTeX

Github contributions (5)

chipsalliance/chisel

Apr 2021 - Oct 2022

Chisel: A Modern Hardware Design Language

Role in this project:

Backend Developer

Contributions:14 reviews, 25 commits, 45 PRs in 1 year 6 months

Contributions summary:Jared primarily contributed to the Chisel hardware design language project by implementing features related to the serialization and compression of file information within the FIRRTL intermediate representation. They also fixed bugs in the parsing and serialization of source locators and memory annotations, improving the reliability of the compiler. Furthermore, the user's work involved adding new APIs for read, write, and readwrite memory accessors for SyncReadMem, enhancing the capabilities of memory operations within the Chisel framework.

chiselhardware-designschisel3scalafirrtl

chipsalliance/firrtl

Apr 2021 - Mar 2022

Flexible Intermediate Representation for RTL

Role in this project:

Back-end Developer

Contributions:4 reviews, 8 commits, 11 PRs in 10 months

Contributions summary:Jared contributed to the `firrtl` repository by implementing and modifying core functionalities related to the intermediate representation and serialization of hardware designs. They added features such as an `indent` parameter to the `Serializer.serialize()` function, improving the flexibility of the serialization process. The user also worked on implementing and fixing bugs in source locator compression, enhancing the efficiency of the file info handling. Furthermore, the user addressed issues related to memory annotation deduplication and multi-module protobuf emission.

representationtransformationintermediate-representationrtlcompiler

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