Jayant Bhardwaj
Senior Principal Engineer at Aricent
Delhi, India
Summary
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Senior🎓
Top SchoolJayant Bhardwaj is a Senior Principal Engineer and system architect with over a decade of experience designing high-performance carrier-grade networking systems, currently shaping MPLS/IP feature and data-plane architectures at Ciena. He specializes in requirements definition, control- and data-plane design for IP/MPLS/GMPLS systems, with hands-on development on Broadcom ARAD and Petra network processors and a strong focus on HA/OpenSAF-compliant chassis architectures. His work spans VPWS/VPLS/MPLS-OAM, RSVP-TE/OSPF-TE control-plane stacks and QoS, and he has deep protocol-level experience from radio access (GSM/GPRS/EDGE RLC-MAC) through core-network interfaces. Jayant combines system-level leadership with delivery discipline, consistently hitting quality and timeline targets while guiding cross-functional teams. A subtle differentiator is his blend of wireless protocol roots and modern packet-switching expertise, enabling pragmatic designs that bridge radio and wireline domains. Based in Delhi, he brings both technical depth and proven execution on complex telecom platforms.
8 years of coding experience
7 years of employment as a software developer
University of Delhi
Sanskrit
Github Skills (5)
typescript1
messaging1
ethereum1
blockchain1
react1
Programming languages (2)
Github contributions (5)
hereisjayant/MeMeow-ML-Cat-Meme-Generator
Apr 2021 - May 2021
Contributions:56 commits, 8 pushes, 1 branch in 1 month
hereisjayant/Resume-Jayant
Aug 2020 - Apr 2022
Contributions:32 pushes, 1 branch in 1 year 8 months
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