Jaymin Patel
Product Development Engineer at Intel Corporation
Austin, Texas, United States
Summary
👤
Senior🎓
Top SchoolJaymin Patel is a Product Development Engineer at Intel with 11 years of experience in ASIC/SoC/FPGA design, validation, and testability, blending hands-on RTL (Verilog/SystemVerilog) with scripting in Python/Perl/TCL. He drives manufacturability and testability from feasibility through production ramp, contributing to timing, power, and DFT optimizations for complex IPs and protocols like PCIe, NVMe, AXI, and SPI. His background includes FPGA characterization and silicon debug using STA, power analysis, and ATE, reflecting a practical bridge between pre-silicon models and real silicon behavior. A San Jose State MS graduate with prior research in nanostructured memories, he combines academic device-level simulation experience with production-focused engineering. Based in Austin, he’s comfortable across EDA toolchains (Synopsys, Cadence, ModelSim, PrimeTime) and brings an uncommon mix of lab-level silicon characterization and scalable design-for-test expertise.
11 years of coding experience
2 years of employment as a software developer
San José State UniversityGujarat Technological UniversityBachelor's degree, Wireless Communication ,Digital Signal Processing, Bachelor's degree, Wireless Communication ,Digital Signal Processing at Kansas State University
English, Gujarati, Hindi
Github Skills (34)
studio10
staging10
luci10
captive10
connection-manager10
openwrt10
wifimanager10
wifi10
captive-portal9
esp82669
feed9
portal9
arduino9
esp328
firmware8
Programming languages (7)
Github contributions (5)
jempatel/packages
Jan 2019 - Apr 2024
Community maintained packages for OpenWrt. Documentation for submitting pull requests is in CONTRIBUTING.md
Contributions:8 PRs, 123 pushes, 13 branches in 5 years 4 months
pull-requestsopenwrt
jempatel/luci
Jul 2018 - Apr 2024
LuCI - OpenWrt Configuration Interface
Contributions:6 PRs, 73 pushes, 4 branches in 5 years 9 months
luciopenwrt
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