Jaymin Patel is a Product Development Engineer at Intel with 11 years of experience in ASIC/SoC/FPGA design, validation, and testability, blending hands-on RTL (Verilog/SystemVerilog) with scripting in Python/Perl/TCL. He drives manufacturability and testability from feasibility through production ramp, contributing to timing, power, and DFT optimizations for complex IPs and protocols like PCIe, NVMe, AXI, and SPI. His background includes FPGA characterization and silicon debug using STA, power analysis, and ATE, reflecting a practical bridge between pre-silicon models and real silicon behavior. A San Jose State MS graduate with prior research in nanostructured memories, he combines academic device-level simulation experience with production-focused engineering. Based in Austin, he’s comfortable across EDA toolchains (Synopsys, Cadence, ModelSim, PrimeTime) and brings an uncommon mix of lab-level silicon characterization and scalable design-for-test expertise.
11 years of coding experience
2 years of employment as a software developer
San José State University
Gujarat Technological University
Bachelor's degree, Wireless Communication ,Digital Signal Processing, Bachelor's degree, Wireless Communication ,Digital Signal Processing at Kansas State University
This repository is a mirror of https://git.openwrt.org/openwrt/openwrt.git It is for reference only and is not active for check-ins or for reporting issues. We will continue to accept Pull Requests here. They will be merged via staging trees then into openwrt.git. All issues should be reported at: https://bugs.openwrt.org
Contributions:6 releases, 3 PRs, 13 pushes in 4 years 6 months
Contributions:6 PRs, 74 pushes, 4 branches in 7 years 5 months
openwrt
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