Jean-Philippe Noel is a research engineer specializing in memory circuit design with over 15 years of experience and 11 years in industry research roles focused on secure data handling, in- and near-memory computing, and emerging non-volatile memories. Based in Greater Grenoble, he blends system-technology co-optimization with hands-on expertise in SRAM, TCAM, FD-SOI and bulk technologies, contributing to patents and a substantial international publication record. His career spans STMicroelectronics and CEA, where he progressed from analog/digital IC design and PhD research to leading memory architecture projects and mentorship of apprentices, interns and doctoral candidates. Jean-Philippe’s background includes UWVR LDPC decoder design and TCAD-driven bitcell optimization, highlighting a rare mix of circuit-level innovation and system-level thinking. He is particularly adept at translating novel device characteristics into practical memory architectures that enhance security and compute efficiency.
11 years of coding experience
9 years of employment as a software developer
Associate's degree, Electrical and Electronics Engineering, Associate's degree, Electrical and Electronics Engineering at IUT de Montpellier-Sète
Doctor of Philosophy - PhD, Microelectronics, Doctor of Philosophy - PhD, Microelectronics at Université Grenoble Alpes
Master of Engineering - MEng, Microelectronics, Telecommunication, Master of Engineering - MEng, Microelectronics, Telecommunication at Polytech Marseille
Master of Science - MS, Microelectronics, Master of Science - MS, Microelectronics at Aix-Marseille Université
Contributions:16 PRs, 230 pushes, 28 branches in 1 year 4 months
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Jean-philippe Noel - Research Engineer In Memory Circuit Design at CEA