Jean-roch Coulon
Risc-V Processor Architect at invia
Meyreuil, Provence-Alpes-Côte d'Azur, France
Summary
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Rockstar🎓
Top SchoolJean-roch Coulon is a RISC-V processor architect with over 6 years focused on CPU microarchitecture and security-focused silicon, currently at Thales Silicon Security in Provence. He brings deep hands-on experience across the full hardware lifecycle—from Verilog changes to instruction queues and AXI memory interfaces to system-level verification and test automation—evidenced by contributions to the widely used CORE-V CVA6 Linux-capable RISC‑V core and its verification infrastructure. His background spans cryptographic IP, smartcard products, and microprocessor design at Gemalto, Invia and STMicroelectronics, where he led projects from RTL design through place-and-route and system verification. He is skilled at bridging architecture and tooling, having refactored verification environments and integrated new simulators to scale test coverage. Comfortable in both research and product engineering contexts, he combines an engineer’s attention to implementation detail with an architect’s view of performance and security trade-offs. Educated at ENSERG in Grenoble, he blends classical microelectronics training with practical embedded systems delivery.
6 years of coding experience
2 years of employment as a software developer
Ingémieur, Electronique et Microelectronique, Ingémieur, Electronique et Microelectronique at Ecole Natrionale Supérieure d'Electronique et de Radioélectricité de Grenoble (ENSERG)
Github Skills (16)
sh10
risc-v10
embedded10
verilog10
verification10
script10
shell10
systemverilog10
sys10
scripting10
uvm10
test-automation10
build-automation9
assembly8
assembler8
Programming languages (6)
Github contributions (5)
openhwgroup/cva6
Feb 2020 - Dec 2022
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:1 release, 181 reviews, 26 commits in 2 years 10 months
Contributions summary:Jean-roch's contributions focused on configuring and modifying the CVA6 core's instruction realign and memory interfaces. They made changes to the instruction queue and the memory system, introducing parameters and functions to improve performance. This involved work in Verilog to define, configure and implement modifications, showing a deep understanding of the core's architecture and the interaction between its various modules.
cpurisc-vasicbootingariane
openhwgroup/core-v-verif
Oct 2020 - Jan 2023
Functional verification project for the CORE-V family of RISC-V cores.
Role in this project:Automation Engineer / Build & Release Engineer
Automation Engineer / Build & Release EngineerContributions:107 reviews, 134 commits, 234 PRs in 2 years 3 months
Contributions summary:Jean-roch primarily contributed to the verification infrastructure of the RISC-V core verification project. Their work involved modifying test scripts (`smoke-tests.sh`, `dv-riscv-tests.sh`, `dv-riscv-compliance.sh`) to integrate new simulators and update test execution. They also refactored the test environment, moving scripts and dependencies to new directories for better organization and maintainability. Furthermore, the user expanded the testing capabilities by including the support for C tests and expanding AXI structure.
risc-vsystemverilogriscverificationcores
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