Jean Wu is a software engineer based in Seattle with a decade of experience building reliable backend systems at Amazon, progressing from intern to full-time engineer. Trained in Electrical and Computer Engineering at the University of Toronto, Jean brings a hardware-aware perspective to software problems and has hands-on experience debugging complex tooling and build infrastructure. Outside of work, Jean contributes to the open-source Verilog-to-Routing (VTR) project, fixing routing-graph edge cases and shoring up buildbot and benchtracker scripts—skills that highlight a knack for low-level correctness and CI robustness. Comfortable navigating large codebases, Jean blends production-focused delivery with attention to test and tooling quality, making him effective at preventing regressions before they reach customers.
10 years of coding experience
2 years of employment as a software developer
Bachelor of Applied Science - BASc, Electrical and Computer Engineering, Bachelor of Applied Science - BASc, Electrical and Computer Engineering at University of Toronto
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Backend Developer
Contributions:130 commits, 1 PR, 96 pushes in 3 months
Contributions summary:Jean primarily focused on modifying and debugging core functions of the Verilog-to-Routing (VTR) flow. They addressed an out-of-bounds index issue in the routing graph and made several attempts to integrate and check the buildbot functionality, fixing broken commits related to build verification. Furthermore, the user adjusted benchtracker scripts for task table naming, indicating work on the build and test infrastructure.
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