Jędrzej Boczar is an Embedded Software Engineer with a decade of experience building low-level firmware and hardware integrations from Wrocław, Poland. He combines FPGA-focused work—contributing SDRAM controllers, DDR training, and board support in the LiteX ecosystem—with practical embedded software improvements such as BIOS and device-tree tooling. At GoodByte and previously at Antmicro and GlobalLogic he has bridged hardware and software, shipping reliable device engineering solutions for IoT and high-performance embedded platforms. Notably, his open-source contributions extend beyond firmware into developer tooling, improving Neovim Treesitter indentation for languages like Python and adding devicetree support, reflecting a pragmatic attention to developer experience as well as hardware reliability.
10 years of coding experience
3 years of employment as a software developer
Inżynier (Inż.), Automatyka i Robotyka, Inżynier (Inż.), Automatyka i Robotyka at Politechnika Wrocławska
Nvim Treesitter configurations and abstraction layer
Role in this project:
Back-end Developer
Contributions:3 reviews, 29 commits, 11 PRs in 1 year 9 months
Contributions summary:Jędrzej primarily focused on enhancing the indentation functionality within the Neovim Treesitter plugin, a configuration and abstraction layer for the tree-sitter parsing library. They introduced new features such as `@return` and `@ignore` to fine-tune indentation behavior, particularly for languages like Python. The commits involved modifying Lua files and Scheme query files to improve the accuracy and flexibility of the indentation rules, thereby improving the user experience. Additionally, they added support for the devicetree parser.
Contributions:66 commits, 32 PRs, 13 comments in 1 year 4 months
Contributions summary:Jędrzej contributed primarily to the embedded systems aspects of the repository, focusing on SDRAM and related memory controllers. The user added functionality to create and configure SDRAM modules using SPD data, enabling more flexible and accurate memory initialization. The user further introduced DQ-DQS training procedures and debugging tools, reflecting a focus on improving memory performance, reliability, and ease of troubleshooting within the context of the FPGA hardware project. The user is also involved in improving the BIOS, which is the software layer for hardware initialization.
vhdlsystem-on-chipedasochardware
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