Jeff Goeders
Associate Professor
Provo, Utah, United States
Summary
🤩
Rockstar🎓
Top SchoolJeff Goeders is an Associate Professor of Computer Engineering at Brigham Young University with 14 years of experience bridging academic research and practical CAD tool development. He specializes in FPGA CAD flows and power estimation, contributing backend and DevOps improvements to the widely used open-source Verilog-to-Routing (VTR) project, including nuanced power-model enhancements for pass transistors. His career blends teaching and research—spanning roles from TA at UBC to industry internships and co-op positions—grounded in a BASc from University of Toronto and graduate studies at UBC. Known for translating complex circuit-level concerns into robust tooling and cluster-ready workflows, he brings both scholarly rigor and hands-on engineering to problems that sit at the intersection of hardware, software, and system performance.
14 years of coding experience
9 years of employment as a software developer
PhD Student, Computer Engineering, PhD Student, Computer Engineering at The University of British ColumbiaBASc, Computer Engineering, BASc, Computer Engineering at University of Toronto
Github Skills (9)
fpga10
python10
eda10
cad10
verilog9
c-language8
build-automation8
devops8
cprogramming-language8
Programming languages (16)
Github contributions (5)
verilog-to-routing/vtr-verilog-to-routing
May 2012 - Nov 2022
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Backend & DevOps Engineer
Backend & DevOps EngineerContributions:6 reviews, 212 commits, 30 PRs in 10 years 8 months
Contributions summary:Jeff contributed to the power estimation tools within the VTR framework. They implemented changes to the architecture generation scripts and made enhancements to the run VTR flow, including updates for the UBC cluster. They also added support for non-minimum sized NMOS pass transistors in the power model and added power related information for each of the port types. The user also appears to be working on the ACE2 branch to update a power estimation tool, adding support for a random seed and fixing some bugs.
cadfpgaverilogvtrplacement
byu-cpe/ecen625
Mar 2021 - Aug 2025
Contributions:81 pushes, 2 branches, 1 comment in 4 years 5 months
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