Summary
Jeffrey Cassidy is a Principal Consultant and FPGA/DSP specialist with 11 years of engineering experience applying high-performance signal processing and computing techniques across video, RF, ultrasound and satellite communications. He combines deep theoretical DSP and applied-math skills with hands-on RTL craftsmanship—Verilog/SystemVerilog/VHDL—and a proven track record of timing closure and hardware-aware optimization on large Xilinx designs. Jeffrey models systems in C/C++, Python/NumPy and Matlab, integrates RTL with software toolchains (Modelsim, Gnuradio), and delivers reusable, parametrized IP for multi-channel, multi-rate applications. His background ranges from academic research at the University of Toronto to commercial projects such as spread-spectrum satellite links and 1M-line UHD broadcast video timing fixes. Outside engineering he is an experienced live-aboard sailing instructor with extensive North Channel knowledge, reflecting a pragmatic, safety-first approach to complex, real-world systems. Colleagues rely on him for rapid, mathematically grounded troubleshooting when projects face tight performance or timing constraints.
11 years of coding experience
3 years of employment as a software developer
Biophotonics, Biophotonics at BiOP '13
PhD, Computer Engineering, PhD, Computer Engineering at University of Toronto
Hillfield-Strathallan College
B.Eng., Electrical Engineering, B.Eng., Electrical Engineering at McGill University
English