Jeffrey Collins
Senior FPGA Engineer at Vector Atomic
Livermore, California, United States
Summary
👤
Senior🎓
Top SchoolJeffrey Collins is a Senior FPGA Engineer based in Livermore, CA with 14 years of experience designing PCBs, FPGA firmware, and embedded software for industrial, automotive LIDAR, medical, and government systems. He combines deep hands-on skills in SystemVerilog/Verilog/VHDL and Xilinx/Altera toolchains with practical embedded C/C++ work on ARM and microcontroller platforms, often owning bring-up, verification, and production release automation. Jeffrey has repeatedly improved CAD and build automation—authoring Altium/Orcad scripts, migration tools, and Jenkins build integrations—and contributed back to community Altium add-ons on GitHub. He is comfortable spanning system architecture through low-level driver and hardware design, and has a track record of making legacy codebases and toolchains more maintainable and auditable. Colleagues rely on him for safety-critical designs (laser/LIDAR and PLD safety zones) and pragmatic engineering leadership across cross-disciplinary teams.
14 years of coding experience
24 years of employment as a software developer
MS (not complete), Electrical Engineering, MS (not complete), Electrical Engineering at University of California, DavisMoreau High School
Github Skills (5)
version-control10
svn10
subversion10
pascal10
scripting10
Programming languages (3)
Github contributions (3)
Altium-Designer-addons/scripts-libraries
Feb 2012 - Dec 2013
Set of community add-ons for Altium Designer
Role in this project:
Back-end Developer
Back-end DeveloperContributions:90 commits in 1 year 10 months
Contributions summary:Jeffrey primarily contributed to enhancing and maintaining the Altium Designer add-ons scripts and libraries. Their work focused on modifying and optimizing the scripts for the release manager to improve the functionality for choosing generate output containers and adding support for excluding subdirectories in the SVN. The changes included modifications to the code to hack OutJob files and also to check in generated files. These commits also demonstrate that the user was adding a new functionality to the existing files.
scriptingadd-onsazerothcoredesignerfootprint
veripool/verilog-mode
Feb 2023 - Feb 2023
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
Contributions:3 comments, 1 issue in 1 day
verilogsystemverilogindentationmastergnu
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