Jens Olson is a Senior Principal Engineer based in San Jose with eight years in his current ML hardware architecture focus and a multi-decade background in processor, GPU, and accelerator design. He specializes in machine learning hardware accelerators, datapath design and Verilog, and has led architecture and implementation for neural-network and speech-recognition co-processor chips that materially improved performance on first silicon. At Arm he drives ML hardware architecture, building on prior principal- and senior-level roles at Samsung, Cypress/Spansion and contractors where he combined system architecture, verification, and FPGA bring-up. His work spans low-level power and ECC-aware controller design to high-level accelerator partitioning, reflecting deep full-chip understanding rather than a narrow RTL focus. Trained at Stanford (MS) and Wisconsin–Madison (BS), Jens pairs academic rigor with practical cross-functional execution across multinational teams. An understated strength is his track record of translating algorithmic needs into silicon-efficient datapaths that halve latency or reduce power in shipping products.
8 years of coding experience
17 years of employment as a software developer
Bachelor of Science (BS) electrical and computer engineering, Bachelor of Science (BS) electrical and computer engineering at University of Wisconsin-Madison
MS Electrical Engineering, MS Electrical Engineering at Stanford University
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