Jeremiah Leary
Staff Electrical Enginner at Collins Aerospace
Cedar Rapids, Iowa, United States
Summary
👤
Senior🎓
Top SchoolJeremiah Leary is a Staff Electrical Engineer with nearly two decades of hands-on ASIC and FPGA design experience, leading multi-disciplinary teams from requirements through wafer probe and system integration. He excels at creating repeatable design flows and automation—authoring tools like a VHDL style-guide enforcer and scripting complex synthesis, verification, and lab-deployment pipelines that cut cycle time and reduce handoffs. Jeremiah has closed timing on multi-million-gate ASICs, pioneered methodologies to enable early post-layout simulation, and devised JIRA-driven Earned Value reporting from Agile data. A proven mentor and program lead, he combines deep physical-design and DFT expertise with practical systems thinking to uncover constraint and modeling errors early. Based in Cedar Rapids, he’s an HDL practitioner who increasingly blends software tooling to ease HDL development and enable full-system verification before hardware exists.
9 years of coding experience
23 years of employment as a software developer
Bachelor of Science in Engineering, Solid State Electronics, Bachelor of Science in Engineering, Solid State Electronics at Arizona State UniversityAssociate of Arts, Associate of Arts at Glendale Community College
Github Skills (32)
suppress10
enforcement10
vhdl10
beautify10
coding10
suppression10
linting10
xilinx8
warnings8
simulator7
verilog7
gcc7
logfile7
hardware6
timing6
Programming languages (3)
Github contributions (5)
jeremiah-c-leary/vhdl-style-guide
Jul 2017 - Jan 2023
Style guide enforcement for VHDL
Contributions:81 reviews, 2257 commits, 630 PRs in 5 years 7 months
vhdlstyleenforcementlintingstyle-guide
jeremiah-c-leary/eda-log-file-warning-suppressor
Apr 2020 - May 2024
Suppresses warnings in EDA logfiles.
Contributions:28 PRs, 114 pushes, 30 branches in 4 years 1 month
patchwarningsvhdlsuppresseda
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