Jérôme Quévremont
RISC-V And Open Hardware Project Leader at OpenHW Group
Orsay, Île-de-France, France
Summary
🤩
Rockstar🎓
Top SchoolJérôme Quévremont is a RISC-V and open hardware project leader at Thales Research & Technology, coordinating corporate RISC-V strategy, FPGA activities, and European collaborative R&D with a hands-on lens for architecture and expertise. With over two decades in SoC/ASIC design, team leadership and trusted computing, he blends deep microelectronics know-how with practical project management across industry consortia. He co-chairs technical working groups at the OpenHW Foundation and vice-chairs the OpenHW Group Cores Task Group, helping shape roadmaps and open-source IP such as the CORE-V family. His contributions to the well-known CVA6 (CVA6) processor documentation—improving virtual memory, programmer view and bit-manipulation guides—underscore a focus on making complex processor features accessible to developers. Based in Orsay, France, he pairs academic roots from Télécom Bretagne / IMT Atlantique with a rare mix of standards, cybersecurity and systems-level design experience. Colleagues describe him as the connector who turns cross-domain research into deployable silicon and open-source ecosystems.
5 years of coding experience
3 years of employment as a software developer
Ingénieur généraliste - Diplôme Télécom Bretagne (MSEE), Computer science, electronics, signal processing, networks, economy. Major in integrated circuits., Ingénieur généraliste - Diplôme Télécom Bretagne (MSEE), Computer science, electronics, signal processing, networks, economy. Major in integrated circuits. at IMT AtlantiqueIngénieur généraliste (MSEE), Computer science, electronics, signal processing, networks, economy. Major in integrated circuits., Ingénieur généraliste (MSEE), Computer science, electronics, signal processing, networks, economy. Major in integrated circuits. at Télécom Bretagne
English
Github Skills (10)
cpu10
risc-v10
rs10
documentation10
systemverilog-hdl9
asic4
ria4
fpga4
aria24
ane4
Programming languages (6)
Github contributions (5)
openhwgroup/cva6
Apr 2022 - Oct 2022
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:
Technical Writer
Technical WriterContributions:93 reviews, 2 commits, 45 PRs in 5 months
Contributions summary:Jérôme primarily contributed to the documentation of the CVA6 processor core. This included creating a requirement specification, a user's guide, and various interface specifications. The user also updated existing documentation, adding sections on virtual memory, the programmer's view, and bit manipulation, improving the overall usability and clarity of the documentation for developers and integrators. The contributions demonstrate a focus on documenting the core's features and functionalities for a broad audience.
cpurisc-vasicbootingariane
jquevremont/core-v-docs
Sep 2020 - Nov 2022
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
Contributions:4 PRs, 34 pushes, 1 branch in 2 years 2 months
risc-vrisccores
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