JesseĀ Cirimelli-low

VLSI-DA Group Member at University of California, Santa Cruz

Belmont, California, United States
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Summary

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Senior
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Top School
Jesse Cirimelli-Low is a PhD candidate in Computer Engineering at UC Santa Cruz with eight years of hands-on experience in VLSI design automation, specializing in SRAM compilers, NVSRAM, and memristive circuits. As a core contributor to the open-source OpenRAM project, he has implemented back-end features like automated datasheet and HTML documentation generation that tie characterization outputs directly into tooling. He blends deep hardware design knowledge with practical software engineering, having led vision and networking code for autonomous ROVs and built automation tools in industry settings. Passionate about education, Jesse has designed and taught maker-style STEM curricula for library patrons and staff, translating complex tech into approachable learning experiences. Based in Belmont, California, he pairs academic research with community-focused outreach, reflecting a commitment to both advancing memory design and growing the next generation of technologists.
code8 years of coding experience
job1 year of employment as a software developer
bookHigh School Diploma, High School Diploma at Junipero Serra High School, San Mateo, California
bookUniversity of California Santa Cruz
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Github Skills (3)

python10
html9
spice8

Programming languages (5)

C#SourcePawnVerilogHTMLPython

Github contributions (5)

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VLSIDA/OpenRAM

Oct 2018 - Dec 2022

An open-source static random access memory (SRAM) compiler.
Role in this project:
userBack-end Developer
Contributions:317 commits, 10 comments, 4 issues in 4 years 3 months
Contributions summary:Jesse's commits show initial work on generating HTML documentation, including generating data sheets for the openRAM SRAM compiler. The user modified parser.py, which included defining classes such as the operating conditions, timing, and deliverable information. They also made changes to OpenRAM's main file (openram.py) to generate the datasheet from characterization of the SRAM created. Furthermore, the user added code to include basic styling within the HTML generation process.
netgenmemorypythongdsmagic
jcirimel/mouse

Jul 2023 - Feb 2025

Contributions:172 pushes, 1 branch in 1 year 7 months
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Jesse Cirimelli-low - VLSI-DA Group Member at University of California, Santa Cruz