Jessica Clarke
Senior Research Software Engineer at University of Cambridge
Cambridge, England, United Kingdom
Summary
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Rockstar🎓
Top SchoolJessica Clarke is a Senior Research Software Engineer and systems security researcher with 14 years of experience, currently working on the CHERI capability architecture at the University of Cambridge. She combines deep low-level expertise across compilers, firmware, and OS ecosystems—contributing to LLVM, GHC, OpenSBI, EDK II, ACPICA and RISC-V tooling—with practical porting and memory-safety work that targets emerging hardware like CHERI. A Debian, FreeBSD and LLVM developer and co-chair of the RISC-V psABI task group, she blends standards-level coordination with hands-on fixes from compiler TableGen to supervisor firmware. Her open-source footprint shows both careful refactors (memory-safety and portability) and pragmatic maintenance (PHP8 compatibility, emulator support), reflecting a rare mix of research rigour and production pragmatism.
14 years of coding experience
3 years of employment as a software developer
St Paul's SchoolDoctor of Philosophy - PhD Computer Science, Doctor of Philosophy - PhD Computer Science at University of Cambridge
Stackoverflow
8,541reputation
689kreached
241answers
18questions
xcode
top-5%
ipad
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iphone
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objective-c
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ios
top-5%
Github Skills (75)
float3210
package-management10
compiler-development10
firmware10
c1110
c1710
code-generation10
dt10
arm10
floating-point10
embedded10
emulation10
haskell10
qemu10
architecture10
Programming languages (39)
Github contributions (5)
riscv/sail-riscv
May 2019 - Nov 2022
Sail RISC-V model
Role in this project:
Back-end Developer
Back-end DeveloperContributions:406 reviews, 24 commits, 27 PRs in 3 years 6 months
Contributions summary:Jessica primarily contributed to the Sail RISC-V model, focusing on improvements to the instruction set architecture. They implemented features to print canonical assembly for immediate loads/stores, and generate correct cause for AMO faults, which involved modifications to the platform and memory model. Furthermore, the user addressed emulator issues, including fixing long option parsing in the C emulator and allowing extensions to provide custom exception codes and page fault causes. They also added support for the D extension.
risc-vriscv32sailriscopenembedded
llvm/llvm-project
Oct 2021 - Oct 2021
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
Role in this project:Backend Developer & System Architect
Backend Developer & System ArchitectContributions:241 reviews, 3 commits, 26 PRs in 5 days
Contributions summary:Jessica contributed to the LLVM project, focusing on low-level compiler and code generation tasks. Their work included fixing inconsistencies in DXIL code, optimizing AMDGPU intrinsics, and preventing errors by restricting pointer types in MVT::getVT and EVT::getEVT. Furthermore, the user addressed a grammar issue in RISCV documentation and improved portability and correctness of the LazyOffsetPtr within the clang compiler. The user also made improvements to the LLVM TableGen system.
compilerstechnologiesclangsubmittoolchain
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