Summary
Jeya K is an Associate Professor in Electronics and Communication Engineering with over 20 years of teaching, research, and academic leadership experience, currently at Kalasalingam University. He specializes in VLSI RTL design, low-power architectures, and FPGA implementations, and holds a PhD focused on optimization algorithms for thermal-aware partitioning and floorplanning of 3D ICs. More recently he has bridged his VLSI expertise into Silicon Photonic IC design, applying AI-driven optimization for IC partitioning, TSV assignment, and photonics-aware architectures. His work spans embedded systems and smart computing, aiming to improve performance and energy efficiency through algorithm-hardware co-design. A proactive mentor and collaborator, he has supervised multiple SCOPUS and WoS publications and regularly engages with industry and academic partners to translate research into practical semiconductor solutions.
10 years of coding experience
Doctor of Philosophy - PhD, Optimization Algorithms for Thermal Aware Partitioning and Floorplanning for 3D ICs, Doctor of Philosophy - PhD, Optimization Algorithms for Thermal Aware Partitioning and Floorplanning for 3D ICs at Kalasalingam University- Electronics and Communication Engineering Department
Master of Engineering (M.Eng.), VLSI Design, Distinction, Master of Engineering (M.Eng.), VLSI Design, Distinction at Arulmigu Kalasalingam College of Engineering AKCE
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering, Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering at Angala Amman College of Engineering AACET
HSC, Maths, Physics, Chemistry, Biology, HSC, Maths, Physics, Chemistry, Biology at S.B.K Boys Higher Secondary School, Aruppukottai
English, Tamil