Summary
Jiahuan Shi is a Senior Verification Manager with nine years of focused experience in SoC verification for Smart TVs, tablets, mobile devices and IP/OTT set-top boxes, now leading Wi‑Fi, Bluetooth and deep learning verification at Amlogic. He brings deep hands‑on expertise in SystemVerilog/Verilog, UVM/VMM, assertions and functional coverage, paired with practical tool experience (VCS, Verdi) and ASIC flow know‑how. Jiahuan’s background spans block-to-system level verification, ATPG pattern generation and verification infrastructure, giving him a rare blend of low‑level debugging and system integration skills. Comfortable scripting and automation with C/C++, Perl and Makefiles, he also leverages solid circuit-level insight to accelerate root-cause analysis. Based in Shanghai, he combines methodical engineering discipline with a pragmatic, life-loving outlook reflected in his GitHub bio: “热爱生活,重新出发.”
9 years of coding experience
8 years of employment as a software developer
Master's degree, Electrical, Electronics and Communications Engineering, Master's degree, Electrical, Electronics and Communications Engineering at Xidian University
English