Jiale Wei
Design Verification Engineer
San Jose, California, United States
Summary
👤
Senior🎓
Top SchoolJiale Wei is a Design Verification Engineer with 11 years' experience across industry leaders including Apple, Huawei, Hikvision and TP-LINK, specializing in SoC/ASIC verification and digital IC design at advanced nodes (7nm, 28nm, 45nm). Proficient in SystemVerilog/Verilog, VHDL, TCL, C/C++, SPICE and Cadence SKILL, he blends hands-on verification (VCS, Fusion Compiler, IC Compiler) with physical verification and static timing analysis expertise. He holds an MS in Electrical Engineering from the University of Minnesota and a BE from Zhejiang University, and his background in both academia and industry lab work informs a methodical approach to corner-case validation and silicon bring-up. Based in San Jose, he brings cross-platform fluency (Unix/Windows) and a track record of shipping silicon-focused features from intern SoC projects to current verification responsibilities at Apple. An underappreciated strength is his comfort moving between RTL-level verification and lower-level SPICE/analog considerations, which helps bridge digital verification and physical implementation teams.
10 years of coding experience
2 years of employment as a software developer
Master of Science - MS, Electric Engineering, 3.92, Master of Science - MS, Electric Engineering, 3.92 at 美国明尼苏达大学双城分校Bachelor of Engineering - BE, Electronic, Bachelor of Engineering - BE, Electronic at 浙江大学
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (36)
tla9
verification9
bluetooth9
specification9
isabelle9
rfc9
trust9
homotopy-type-theory8
embedded8
smt8
proofs8
sat-solver8
model-checking8
coq8
proof8
Programming languages (3)
Github contributions (5)
LVPGroup/arinc653model
May 2015 - Dec 2016
Contributions:13 commits, 12 pushes, 1 branch in 1 year 6 months
LVPGroup/lvpgroup.github.io
Jul 2018 - Feb 2025
Contributions:143 pushes, 1 branch in 6 years 8 months
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