Jiangheng Lu
Principal Design Engineer at Celestica
Fremont, California, United States
Summary
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Senior🎓
Top SchoolJiangheng Lu is a Principal Design Engineer in Fremont with 11 years of hands-on experience designing high-density power electronics and rack-level power delivery for AI data centers. He holds a PhD in Power Electronics from the University of Maryland and has delivered MHz GaN-based onboard chargers, 800V HVDC modules, hot-swap controllers, and power distribution boards across academia and industry. Comfortable spanning hardware, control, and firmware, he blends prototype-driven R&D with product-definition and market analysis—from EV charging systems to consumer power and data-center HVDC solutions. His career moves between university labs and fast-paced industry teams reflect a knack for turning advanced research into manufacturable, high-performance products. Based in the Bay Area, he combines technical depth with pragmatic deployment experience in emerging AI infrastructure power systems. An inquisitive engineer, he also brings low-level design skills (PLL in Verilog) and a concise, iterative approach to solving thermal, efficiency, and reliability challenges.
11 years of coding experience
10 years of employment as a software developer
Doctor of Philosophy (PhD), Power Electronics, Doctor of Philosophy (PhD), Power Electronics at University of MarylandBachelor's degree, Electrical and Electronics Engineering, Bachelor's degree, Electrical and Electronics Engineering at Huazhong University of Science and Technology
Chinese, English
Github Skills (4)
package-control6
python1
directions1
kubernetes1
Programming languages (1)
Github contributions (5)
junglefive/junglefive.github.io
Sep 2017 - Oct 2017
Contributions:109 commits, 7 PRs, 104 pushes in 26 days
junglefive/ChipseaAssembly
Mar 2017 - Mar 2018
Contributions:21 releases, 46 pushes, 5 branches in 1 year
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