Jiawei Zhang
FPGA Design Engineer at Huawei
Wuhan, Hubei, China
Summary
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Senior🎓
Top SchoolJiawei Zhang is an FPGA design engineer with 9 years of hands-on experience in VLSI high-volume manufacturing test and FPGA RTL design, currently driving functional spec, microarchitecture, RTL development and verification for optical transmission products at Huawei. He brings deep expertise in high-speed SerDes and mixed-signal validation from prior roles at Intel where he led wafer-sort and HVM transceiver projects for Stratix10 and co-authored work on sampler offset calibration and manufacturing cost optimization. Skilled at end-to-end HVM test methodology, hardware/software infrastructure setup, and yield/time/cost improvements, he combines practical lab debug skills with statistical process analysis. Educated with an MS from USC and a BS in Optics from HUST, he also has CDN-focused internship experience at Tencent, reflecting a broader interest in systems beyond silicon. Colleagues rely on him for bridging device-level analog calibration and digital verification to deliver production-ready transceiver IP.
9 years of coding experience
3 years of employment as a software developer
Master of Science (MS), Electrical and Electronics Engineering, 4.0/4.0, Master of Science (MS), Electrical and Electronics Engineering, 4.0/4.0 at University of Southern CaliforniaBachelor of Science (B.S.), Optics/Optical Sciences, 87.5/100, Bachelor of Science (B.S.), Optics/Optical Sciences, 87.5/100 at Huazhong University of Science and Technology
English, Chinese, JapaneseProgramming languages (1)
Github contributions (5)
AzureGreen/InjectCollection
Oct 2016 - Apr 2017
Contributions:17 commits, 14 pushes, 1 branch in 5 months
AzureGreen/ArkProtect
Apr 2017 - Jul 2017
Contributions:28 commits, 7 pushes, 1 branch in 2 months
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