Jie Chen
IC Design & Verification Engineer
Grenoble, Auvergne-Rhône-Alpes, France
Summary
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Rockstar🎓
Top SchoolJie Chen is an IC Design & Verification Engineer based in Grenoble with 8 years of hands-on experience developing and validating low-power IoT processors and peripherals. At GreenWaves Technologies they led ARM Mbed OS porting for GAP8/GAP9, designed and verified IP blocks (instruction cache, UART, OSPI, HyperBus) and implemented SoC testbenches and FPGA prototypes. Jie combines RTL/SystemVerilog verification skills with embedded C software experience from earlier roles, enabling seamless hardware-software integration from silicon bring-up to developer APIs. An active contributor to the open-source CV32E40P RISC-V core, Jie has improved pipeline behavior, floating-point latencies and debug traceability—showing expertise in both processor microarchitecture and practical FPGA constraints. Their dual French and Chinese engineering education underpins a pragmatic, cross-cultural approach to complex SoC problems.
8 years of coding experience
1 year of employment as a software developer
Master’s Degree, SESI ( Electronic System and Computer Science), Master’s Degree, SESI ( Electronic System and Computer Science) at Université Pierre et Marie Curie (Paris VI)Bachelor’s Degree, Electrical and Electronics Engineering, 87 / 100, Bachelor’s Degree, Electrical and Electronics Engineering, 87 / 100 at 東南大學Master's degree, System on Ship (SoC), 3.7/4.0, Master's degree, System on Ship (SoC), 3.7/4.0 at Telecom ParisTech
Chinese, English, French
Github Skills (7)
risc-v10
cpu-architecture10
embedded10
verilog10
systemverilog10
sys10
fpga9
Programming languages (5)
Github contributions (5)
openhwgroup/cv32e40p
Nov 2018 - Oct 2019
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:7 commits, 6 pushes, 5 tags in 11 months
Contributions summary:Jie primarily contributed to the CV32E40P RISC-V CPU project by modifying the core CPU's behavior and architecture. Their work involved updating the RISC-V pipeline, including changes to floating-point operation latencies, and clearing the xcause register during xret instructions. The user also addressed hardware-related issues, such as deleting unused parameters to avoid FPGA conflicts and updating BIST wrappers for register file testing. Finally, the user modified trace logs for improved debugging and analysis.
risc-vcpupulpuvmriscv
GreenWaves-Technologies/mbed-os
Jul 2018 - Jul 2019
Contributions:8 releases, 79 commits, 169 pushes in 1 year
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