Jihong Min
매니저 at Telechips, Inc.
Kwangju, Gyeonggi, South Korea
Summary
👤
Senior🎓
Top SchoolJihong Min is an IP design manager at Telechips with 8 years of embedded and hardware engineering experience, specializing in HLS-based IP blocks, Catapult HLS, and FPGA/MCU platforms (STM32, ATmega, ESP, nRF). He accelerates verification with Veloce emulation, performs power analysis integrated with PowerPro, and builds virtual platforms in SystemC for early validation. His work spans computer vision and graphics—developing a 3D Surround View GPU renderer and calibration GUIs using OpenCV and OpenGL—and he holds a registered patent related to his field. Prior roles include surgical-robotics hardware and VR peripheral embedded development, reflecting a knack for translating research-grade designs into robust product-ready systems. Based in Gwangju, South Korea, he pairs hands-on implementation skills with a systems-level view of performance and power optimization.
8 years of coding experience
2 years of employment as a software developer
석사, Electrical and Electronics Engineering, 석사, Electrical and Electronics Engineering at 단국대학교Entrepreneurship Courses, Entrepreneurship Courses at Kauffman FoundationGithub contributions (5)
dk-min/verilog_study
Dec 2021 - Jul 2022
Contributions:25 commits, 23 pushes in 6 months
dk-min/vimrc-setting
Apr 2022 - Feb 2024
Contributions:1 push, 1 branch in 1 year 10 months
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