Jim Lewis
Director Of VHDL Training at OSVVM
Tigard, Oregon, United States
Summary
👤
Senior🎓
Top SchoolJim Lewis is a veteran VHDL authority and founder of SynthWorks, bringing over three decades of hands-on ASIC/FPGA design, verification, and training experience. As chief architect of OSVVM and chair of the IEEE 1076 VHDL working group, he has driven open-source verification tooling and standards improvements that let VHDL match capabilities often associated with SystemVerilog+UVM. He leads VHDL education and methodology consulting, having supported high-profile programs like the F-22 ASIC development and complex video codec ASICs, and routinely tackles the toughest verification challenges. Known for creating constrained-random, coverage-driven testbenches and robust verification data structures in VHDL, he blends deep engineering craftsmanship with community-building through IEEE and OSVVM. Based in Tigard, Oregon, he pairs technical leadership with less-expected pursuits such as yoga instruction, reflecting a pragmatic, human-centered approach to mentoring and problem solving.
10 years of coding experience
12 years of employment as a software developer
MS EE, MS EE at Purdue University
Github Skills (108)
simulation-modeling10
simulator10
coverage10
gcc10
vhdl10
ghdl10
uart10
simplify10
tedious10
methodology10
testbench10
tcl10
tlaplus10
memory-model10
verification10
Programming languages (10)
Github contributions (5)
OSVVM/OSVVM
Jan 2016 - Jan 2023
Contributions:4 releases, 21 reviews, 374 commits in 7 years 1 month
memoryvhdlalertssimulationmethodology
OSVVM/UART
Jun 2019 - Nov 2022
Contributions:76 commits, 3 PRs, 133 pushes in 3 years 6 months
injectionstoptransmitterreceiverbreak
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.