Jim Shu is a QEMU system modeling engineer with 12 years in software engineering and a focused decade-plus on RISC-V systems and firmware. Currently at SiFive, he builds QEMU functional models for CPU ISA, privileged architectures, and peripheral IPs to accelerate system software on FPGA platforms. Previously at Andes Technology he ported and maintained RTOSes (FreeRTOS, Zephyr, RT-Thread), developed CMSIS-style baremetal drivers and an Eclipse-based FreeRTOS tracer, and brought Arduino support to RISC-V targets. His background blends deep low-level expertise—cache coherence, baremetal drivers, SPI/PWM/watchdog—with formal academic training (M.S. in Computer Science and Engineering from 國立交通大學). Jim is comfortable bridging hardware and software teams to turn architectural specs into reliable simulation models that unblock firmware development. Colleagues value his pragmatic approach to complex cross-layer problems and his knack for turning peripheral quirks into repeatable testable models.
12 years of coding experience
4 years of employment as a software developer
Master's degree, Computer Science and Engineering, Master's degree, Computer Science and Engineering at 國立交通大學
Contributions:2 releases, 1 push, 3 tags in 5 years
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