Jinfu L is a Principal Engineer based in San Jose with over a decade of hands-on experience designing and bringing up high-speed ASIC and SSD interfaces, specializing in PCIe, UCIe, and memory controller resource management. He has driven silicon bring-up and IP integration across roles at SK hynix, Western Digital, ScaleFlux and Marvell, owning datapath, command scheduling, and power/buffer resource engines for SSD controllers. Known for pragmatic problem-solving in performance-critical designs, he pairs RTL and system-level expertise with FPGA validation and compliance work. Currently focused on die-to-die UCIe and PCIe Gen6 interconnects, he brings rare cross-domain depth from servo firmware and production yield improvements to cutting-edge interconnect architectures.
10 years of coding experience
12 years of employment as a software developer
master Electrical Engineering, master Electrical Engineering at University of Southern California
Contributions:66 commits, 4 PRs, 32 pushes in 9 months
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