Joel Holdsworth
Principal Firmware Engineer at NVIDIA
Campbell, California, United States
Summary
🤩
Rockstar🎓
Top SchoolJoel Holdsworth is a Principal Firmware Engineer with 19 years of experience building embedded systems and firmware, currently driving low-level software at NVIDIA while running his own engineering consultancy. He combines deep C/C++/Python skills, Linux and open-source expertise with electronics and mechanical design training from an MEng at Imperial College. Joel is a pragmatic problem-solver who has improved toolchain compatibility in the Zephyr RTOS, enhanced media streaming and proxy support in the widely used Kodi project, and contributed practical fixes across Git, Wine and FPGA tooling. Comfortable across hardware and software boundaries, he often tackles portability and performance edge cases—modernizing legacy code and improving cross-platform robustness. Based in Campbell, California, he blends principal-level architecture work with hands-on contributions that keep complex embedded products shipping.
18 years of coding experience
Master of Engineering (MEng) Mechanical Engineering, Master of Engineering (MEng) Mechanical Engineering at Imperial College London
English
Stackoverflow
363reputation
41kreached
0answers
6questions
Github Skills (65)
verilog10
python10
wp-api10
proxy10
c1110
winapi10
gcc10
subprocess10
c1710
media-player10
cplus10
file-processing10
embedded10
cpp10
ws-api10
Programming languages (24)
Github contributions (5)
YosysHQ/icestorm
Oct 2015 - May 2018
Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:5 commits, 1 PR, 1 comment in 2 years 6 months
Contributions summary:Joel primarily contributed to the `iceprog` tool, which appears to be used for programming Lattice iCE40 FPGAs. Their commits focused on improving the usability and functionality of the tool, including adding support for reading and writing data to pipes, printing status messages to stderr, and enhancing the help message. Further contributions include allowing truth tables to be specified as an init string and accepting device types like HX1K in `icebox_hlc2asc.py`.
vivadofpgasxilinxlatticeicestorm
verilog-to-routing/vtr-verilog-to-routing
Apr 2018 - Apr 2018
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:Backend Developer
Backend DeveloperContributions:10 commits, 2 PRs, 4 comments in 4 days
Contributions summary:Joel primarily focused on code cleanup, including removing trailing whitespace and replacing line endings. They also addressed minor code style issues, such as replacing smart quotes. The user made changes to various C++ source files within the project, fixing typos related to the declaration of variables, demonstrating a focus on code quality and maintainability. These changes likely involved refactoring and improving the overall codebase structure.
vtrcadedaplacementsynthesis
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