VP GM, Hard IP And Test Chip Development, Central Engineering at Intel Corporation
Fort Collins, Colorado, United States
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Summary
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Senior
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Top School
John Cloudman is a seasoned silicon and platform engineering executive with over 20 years of experience leading global teams to deliver analog/hard IP, high-speed I/O, memory interfaces, power delivery and test-chip solutions from pathfinding through post-silicon support. As VP/GM at Intel he has driven strategy, execution and roadmaps for datacenter, AI, network and edge platforms, launching multiple server SOCs and Ethernet products across advanced nodes. He excels at aligning multi-disciplinary organizations and >$1B portfolios to improve time-to-market and execution quality while retaining deep technical credibility in mixed-signal, physical design and process interactions. Based in Fort Collins, he combines operator-level delivery—having managed tape-ins and production qualification—with a consistent track record of building teams that scale globally and mentor the next generation of engineers. An interesting through-line: he pairs program-level portfolio leadership with hands-on ownership of analog IP performance and process feedback across 10nm–5nm technology nodes.
9 years of coding experience
22 years of employment as a software developer
Bachelor of Science Electrical and Computer Engineering, Bachelor of Science Electrical and Computer Engineering at Rice University
plane.watch feeder client, as a multi-arch docker container.
Contributions:2 pushes in 3 days
feederdockermulti-archplanedocker-container
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John Cloudman - VP GM, Hard IP And Test Chip Development, Central Engineering at Intel Corporation