John Rose
Product Engineering Group Director at Cadence Design Systems
Longmont, Colorado, United States
Summary
👤
Senior🎓
Top SchoolJohn Rose is a Product Engineering Group Director with over three decades of hands-on experience in Verilog and SystemVerilog and 16 years in senior product roles at Cadence Design Systems. He leads engineering teams focused on SystemVerilog and SystemC solutions for complex design and verification challenges, and has deep expertise building VPI applications in C/C++ to solve customer-specific verification problems. A principal developer in early UVM and long-time contributor to verification libraries and tooling, he combines prototype-driven innovation (capture/replay, dynamic test) with customer-facing technical advocacy. Based in Longmont, Colorado, he pairs low-level simulator and PLI/VPI experience with a talent for translating complex EDA concepts into practical, deployable workflows that accelerate customer adoption.
16 years of coding experience
28 years of employment as a software developer
University of Kansas
Github Skills (3)
verification9
methodology9
systemverilog8
Programming languages (1)
Github contributions (1)
Freecellera/freecellera-uvm
Apr 2010 - May 2011
Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)
Contributions:423 commits in 1 year 1 month
accelleraverification-librarysystemveriloguniversal-verification-methodologymethodology
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