Jonathan Drolet
Senior FPGA Designer at RIEDEL Communications GmbH & Co. KG
Montreal, Quebec, Canada
Summary
🤩
Rockstar🎓
Top SchoolJonathan Drolet is a Senior FPGA Designer based in Montreal with 11 years of experience delivering signal-processing and hardware-accelerated solutions across aerospace, broadcasting, and GNSS domains. He has led DO-254 level A implementations, multi-constellation GNSS receivers, and Reed–Solomon decoders, pairing rigorous requirements/test documentation with hands-on SystemVerilog and UVM verification. At RIEDEL and previously at CMC Électronique and Dextera Labs he has driven RF/hardware-software integration and embedded bare-metal systems, bringing algorithms from prototype to certified product. He also contributes to open-source tooling—improving Windows build and test infrastructure for the well-known Verible SystemVerilog toolset—demonstrating cross-platform build and DevOps fluency. Comfortable from low-power ASIC prototyping to high-throughput FPGA designs, he blends deep algorithmic insight with practical productionization experience. Colleagues describe him as a detail-oriented engineer who writes clear requirements and test plans as reliably as synthesizable RTL.
11 years of coding experience
2 years of employment as a software developer
B. Ing, Electrical and Electronics Engineering, B. Ing, Electrical and Electronics Engineering at Université de Montréal - Ecole polytechnique de Montréal
French, English
Github Skills (14)
windows10
systemverilog10
bazel10
build-automation10
testing10
cicd9
bison9
flex9
formatter8
formatters8
parserator7
parser7
linter7
language-server-protocol5
Programming languages (10)
Github contributions (5)
chipsalliance/verible
Apr 2021 - Feb 2022
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Role in this project:
DevOps Engineer & SystemVerilog Developer
DevOps Engineer & SystemVerilog DeveloperContributions:22 reviews, 44 commits, 21 PRs in 9 months
Contributions summary:Jonathan primarily contributed to improving the build and test infrastructure for the Verible project, specifically focusing on Windows compatibility. Their commits include adding support for Windows-specific build tools like win\_flex\_bison, fixing tests to run correctly on Windows, and updating scripts for cross-platform consistency. Furthermore, the user made code adjustments to ensure the project's compatibility with different string view implementations on the Windows platform.
lintersystemverilogdeveloper-toolsparserformatter
corco/verible
Mar 2021 - Mar 2024
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
Contributions:84 pushes, 26 branches in 3 years
systemverilog-developerlinterstyle-parserstyle-lintersystemverilog
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