Jonathon Pendlum
Principal Engineer at NI (National Instruments)
Tokyo, Japan
Summary
🤩
Rockstar🎓
Top SchoolJonathon Pendlum is a Principal Engineer based in Tokyo with 13 years of experience specializing in FPGA-accelerated software defined radio and low-level embedded drivers. He has led RFNoC FPGA development at Ettus Research, contributed core Verilog infrastructure and SystemVerilog testbenches, and improved the USRP hardware driver and FPGA toolchain used by a broad open-source SDR community. As an independent contractor he delivered real-time OFDM modems and drone downlink receivers on Zynq platforms, blending FPGA acceleration, C++ and Python to meet tight performance constraints. Now at National Instruments he continues to drive complex FPGA and embedded system designs at scale, pairing deep hardware expertise with customer-facing mentorship and technical outreach. An understated strength is his track record of shipping production-ready signal processing blocks and toolchain upgrades that resolve subtle timing and clocking issues few engineers enjoy debugging.
13 years of coding experience
15 years of employment as a software developer
Master's degree, Computer Engineering, Master's degree, Computer Engineering at Northeastern UniversityB.S., Electrical Engineering, B.S., Electrical Engineering at Purdue University
Github Skills (17)
verilog10
c-language10
sdl10
driver10
sys10
fpga10
embedded10
vivado10
uhd10
cprogramming-language10
signal-processing9
digital-signal-processing9
spi9
hal8
abstraction-layer8
Programming languages (4)
Github contributions (5)
EttusResearch/fpga
Jul 2014 - Sep 2020
The USRP™ Hardware Driver FPGA Repository
Role in this project:
Embedded Systems Engineer / FPGA Developer
Embedded Systems Engineer / FPGA DeveloperContributions:537 commits, 10 PRs, 34 pushes in 6 years 3 months
Contributions summary:Jonathon primarily focused on modifying and improving the FPGA code within the USRP™ Hardware Driver FPGA Repository. Their contributions involved addressing timing issues in the DAC interface, upgrading the Vivado toolchain, and enhancing the clock generation for the catcodec. They also addressed and corrected various issues in the source code, like correcting transfer types.
xilinxlatticeusrphardwarefpga
EttusResearch/uhd
Sep 2014 - Feb 2022
The USRP™ Hardware Driver Repository
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:75 commits, 14 pushes, 2 branches in 7 years 6 months
Contributions summary:Jonathon primarily focused on low-level hardware driver development and optimization within the USRP™ Hardware Driver. Their contributions included modifications to the e300 module, addressing issues related to RX/TX switch settings, timing in the FPGA capture interface, and minimum clock rate restrictions. Furthermore, the user added a shutdown option to the SPI core and made adjustments to the GPIO core. They also added an option for safe SPI and did a check for reading the chip ID in the ad9361 driver.
driverusrphardwaresdruhd
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.