joonho hwangbo
Computer Scientist at ucb-bar
Berkeley, California, United States
Summary
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Rockstarjoonho hwangbo is a computer scientist and Ph.D. student at UC Berkeley with six years of hands-on experience building and architecting hardware-software systems. He has been a key contributor to prominent open-source RISC-V projects like Chipyard and Rocket Chip, focusing on integrating accelerators and enhancing core debugging capabilities. His work spans system and software architecture, build infrastructure refactoring, and low-level core instrumentation—skills that bridge research prototypes and production-ready SoC flows. Based in Berkeley, he blends academic rigor with practical engineering, regularly modifying build scripts, FIRRTL integration, and debug modules to improve developer productivity and observability. Notably, his contributions include adding hardware ROB debugging and queue metrics tracing, revealing a knack for making opaque microarchitectural behavior transparent. He brings a pragmatic, systems-first approach to complex computer architecture problems, with a talent for making intricate hardware features accessible to software and toolchains.
6 years of coding experience
Github Skills (12)
rt10
debugging10
risc-v10
debug10
accelerator10
rocket-chip10
chisel10
scala9
hardware-designs9
firrtl9
verilog8
configuration-management8
Programming languages (11)
Github contributions (5)
ucb-bar/chipyard
Oct 2022 - Jan 2023
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Role in this project:
System Architect / Software Architect
System Architect / Software ArchitectContributions:1 release, 90 reviews, 48 commits in 3 months
Contributions summary:Joonho made significant contributions to the Chipyard framework, primarily focusing on integrating and configuring new hardware accelerators like Mempress. They modified configuration files, build scripts, and documentation to incorporate these accelerators into various RocketChip-based SoC configurations. The user also refactored build processes, including integrating LowFIRRTL and fixing compilation flags, demonstrating a focus on the overall system architecture and build infrastructure.
rtlout-of-orderhardware-designsvlsicomputer-engineering
chipsalliance/rocket-chip
Mar 2023 - May 2024
Rocket Chip Generator
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:1 review, 14 PRs, 4 comments in 1 year 1 month
Contributions summary:Joonho primarily contributed to the Rocket Chip Generator project by enhancing the debugging capabilities of the core. They added features to trace register writeback values, implemented a hardware ROB debugger and integrated a counter for queue metrics within the DebugROB module. Furthermore, the user made modifications related to debug ROB parameters, configuration settings and made code adjustments in core files to improve debugging functionalities.
rtlriscvchipchiselscala
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