Jordi Merou is an embedded software engineer based in France with 15 years of hands-on experience building and integrating firmware, FPGA toolchains, and embedded Linux ecosystems. He contributes actively to prominent open-source projects—improving STM32 tooling in stlink, extending FPGA backends and build automation in edalize and Silice, and adding board/platform support across LiteX and Buildroot—demonstrating deep hardware-software co-design skills. Jordi excels at making complex toolchains and flashing flows reliable across diverse devices, from Zynq and EOS-S3 to icebreaker and CrossLink platforms. Colleagues rely on him for low-level debugging, flash and register fixes, and automating repeatable builds that bridge development and production. Notably, his work often focuses on practical platform enablement and build integration rather than high-level features, turning fragmented hardware support into reproducible workflows.
Contributions:61 reviews, 33 commits, 86 PRs in 2 years 10 months
Contributions summary:Jordi contributed to the development of hardware definition files (platforms) for various FPGA-based boards within the LiteX-Boards repository. Their work included defining pin assignments, connectors, and other board-specific configurations. They added support for new boards, such as the Red Pitaya and Runber, and also addressed issues and made improvements to existing platform files. The user’s contributions are focused on the low-level hardware aspects of several different FPGA development boards.
Contributions:7 commits, 9 PRs, 14 comments in 2 years 6 months
Contributions summary:Jordi contributed to the edalize library by adding support for new FPGA toolchains and improving existing ones. They integrated Lattice Radiant support by developing a new backend and implemented features for CologneChip GateMate. Additionally, the user fixed initialization issues and improved the Yosys integration, which involved modifying templates and build processes. These changes enhanced the library's compatibility and functionality for various FPGA design flows.
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