Jose Cueva
Digital IP ASIC Verification
Lund, Sweden
Summary
👤
Senior🎓
Top SchoolJose Cueva is a seasoned IC verification engineer with nine years of hands-on experience validating digital and mixed-signal IPs and SoCs, currently focusing on digital IP ASIC verification at Ericsson. He brings deep expertise in SystemVerilog/UVM, Verilog-AMS, formal verification, and AMBA/AXI protocol validation, complemented by scripting skills in Python, Bash and Tcl for regression and coverage automation. His background spans memory and power-management IPs, behavioral analog modeling, and end-to-end simulation using Cadence and Synopsys toolflows. Notably, he blends low-level C test-pattern development with formal unreachability and assertion work, enabling both functional and safety-driven verification closure. Based in Lund, Sweden, Jose combines practical lab training from CTI Renato Archer with enterprise verification experience at NXP, Freescale and Ericsson, delivering pragmatic solutions across mixed-signal verification challenges.
9 years of coding experience
5 years of employment as a software developer
IC Development training, Cadence tools, Microeletronics, IC Development training, Cadence tools, Microeletronics at CTI Renato ArcherBachelor's degree, Electronic Engineering, Bachelor's degree, Electronic Engineering at Universidad Nacional del Altiplano
Spanish, English, aymara
Github Skills (18)
integrate10
connected10
alexa-voice-service10
commercial8
sdk8
device-management8
addin7
makers7
64-bit6
syntax-highlighting6
onenote6
cups5
code-snippets5
32-bit3
printer3
Programming languages (3)
Github contributions (5)
joselcuevam/timer
Jul 2018 - Aug 2022
Contributions:37 commits, 31 pushes, 1 branch in 4 years 2 months
joselcuevam/pyimage
Nov 2016 - Nov 2019
Contributions:10 pushes, 1 branch in 3 years
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