Digital Design Engineer at NHanced Semiconductors, Inc.
Greater Chicago Area United States
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Summary
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Senior
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Joseph Bellahcen is a Digital Design Engineer with eight years of hands-on experience designing and verifying FPGA architectures and embedded systems, currently pursuing integrated BS/MS degrees in Intelligent Systems Engineering at Indiana University Bloomington. He has led pre-silicon SoC verification efforts and implemented SystemVerilog/UVM testbenches, while driving team-level process improvements and an Agile transition as Scrum Master. His work spans radiation-hardened FPGA design with industry partners (QuickLogic, SkyWater, NSWC Crane) and developing internal synthesis/simulation toolchains built on OpenFPGA and Cadence. Joseph combines low-level embedded firmware prototyping (RP2040, STM32) and JTAG/SWD tooling with ASIC floorplanning and encryption-focused research (AES, ASCON, Grain, Xoodyak). Outside core engineering he manages student teams, maintains automated verification infrastructures, and pursues portrait photography and spelunking, reflecting a knack for technical leadership paired with creative, hands-on problem solving.
8 years of coding experience
4 years of employment as a software developer
Master's degree Intelligent Systems Engineering - Computer Engineering, Master's degree Intelligent Systems Engineering - Computer Engineering at Indiana University Bloomington
Contributions:9 PRs, 61 pushes, 26 branches in 1 month
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