Summary
Joseph Constantino is a Senior Hardware Engineer based in Sydney with nine years of experience designing high-speed FPGA and mixed-signal systems for broadcast and RF products. He specializes in area-optimized, real-time video processing IPs (up to 48 Gbps), codec and SMPTE protocol work, and end-to-end FPGA flows from algorithm modeling in C/Python to VHDL RTL, synthesis, and hardware verification. His background includes analog IC design and low-power sub-GHz RF development at Analog Devices, giving him rare cross-domain expertise across analog, digital, and system-level integration. Known for mentoring engineers and shipping complex products, he combines practical board-level debugging and HW–SW Zynq experience with a curiosity for exploring new algorithms for future projects.
9 years of coding experience
6 years of employment as a software developer
Bachelor’s Degree, Computer Engineering, Bachelor’s Degree, Computer Engineering at University of the Philippines
English, Filipino