Joseph Greathouse is a Fellow and software architect at AMD with a decade of experience specializing in the hardware/software interface for high-performance GPU compute. He designs hardware-visible features, architects firmware and software for AMD Instinct accelerators (MI200/MI300), and drives performance and power optimizations across ROCm, including backend contributions to the HIP portability layer. His background blends academic research—PhD work on hardware mechanisms to speed dynamic analyses and published power/performance modeling—with practical product delivery from pre-silicon RTL fixes to post-silicon software tuning and customer enablement. Joseph is known for making hardware do “new and unintended things,” creating novel APIs and workarounds that bridge architecture and real-world workloads. Based in Austin, he pairs deep systems-level research with hands-on engineering to push GPU compute performance, stability, and energy efficiency.
10 years of coding experience
15 years of employment as a software developer
Ph.D., Computer Science and Engineering, Ph.D., Computer Science and Engineering at University of Michigan
HIP: C++ Heterogeneous-Compute Interface for Portability
Role in this project:
Back-end Developer & Performance Engineer
Contributions:1 review, 11 commits, 11 PRs in 2 years 1 month
Contributions summary:Joseph primarily contributed to fixing bugs and improving the performance and stability of the HIP (Heterogeneous-Compute Interface for Portability) project. They addressed issues in occupancy calculations, specifically related to identifying the maximum number of active blocks per multiprocessor, and improved the accuracy of shared memory attribute reporting. The user also fixed issues with cooperative launch APIs, ensuring correct error handling and logging. In addition, the user implemented and tested funnel shift operators.
Contributions:40 commits, 19 PRs, 31 pushes in 3 years 8 months
rocm
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